Interconnect structure containing various capping materials for electrical fuse and other related applications, and design structure thereof

ABSTRACT

A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

FIELD OF THE INVENTION

The invention relates to FINFET and method manufacture, and moreparticularly, to a design structure for interconnect structurescontaining various capping materials for electrical fuses and otherrelated applications.

BACKGROUND

A fuse is a structure that is blown in accordance with a suitableelectrical current. For example, an electrical current is providedthrough the fuse to eventually provide an open circuit condition. Inintegrated circuitry memory devices, fuses can be used for activatingredundancy in memory chips and for programming functions and codes inlogic chips. Specifically, dynamic random access memory (DRAM) andstatic random access memory (SRAM) employ fuses for such purposes.

Electronic fuses can also be used to prevent reduction of yield, whichmay be caused by random defects, generated in the manufacturing process.Moreover, fuse links provide for voltage options, packaging pin outoptions, or any other option desired by the manufacturer to be employedprior to the final processing. This helps increase yield and makes iteasier to use one basic design for several different end products.

Some electrically blowable fuses take advantage of the electromigration(EM) effect to open an electrical connection. For example, EM is thetransport of material caused by the gradual movement of ions in aconductor due to the momentum transfer between conducting electrons anddiffusing metal atoms. In electrically blowable fuses that takeadvantage of EM effect, such transport of material caused by the gradualmovement of ions can open the electrical connection.

However, in a typical e-fuse the EM effect causes undesirable hillocks.More specifically, known e-fuses comprise a two-dimensional dog-boneshape having a small cross-sectional area between large cathode andanode pads. During programming, voids form at the center fuse elementdue to high current density, and eventually create an electrically opencircuit. However, the electromigration causes the conductive material topile-up and form hillocks at the anode end of the fuse element. Hillockformation is an undesirable effect that has not been exploited for anyuseful purpose.

Accordingly, there exists a need in the art to overcome the deficienciesand limitations described hereinabove.

SUMMARY

In a first aspect of the invention, a structure comprises a firstinterconnect structure having a first interfacial structure and a secondinterconnect structure adjacent to the first structure. The secondinterconnect structure has second interfacial structure different fromthe first interfacial structure.

In another aspect of the invention, a structure comprises a wiringinterconnect structure having an interface comprising a metal wiringlayer and a capping layer of a first material type. The structurefurther comprises an electronic fuse interconnect structure having aninterface comprising a metal wiring layer and a capping layer of asecond material type.

In yet another aspect of the invention, a structure comprises a firstmacro having a metal wiring layer on a first level electricallyconnected to a metal wiring layer on a second layer and a capping layerover the metal wiring layer on the second layer which has a firstelectromigration (EM) resistance. The structure further comprises asecond macro adjacent the first macro. The second macro has a metalwiring layer on the first level electrically connected to a metal wiringlayer on the second layer and a capping layer over the metal wiringlayer on the second layer which has a second electromigration (EM)resistance different from the first electromigration (EM) resistance.

In still a further aspect of the invention, an interconnect structurecomprises a first macro having a first e-fuse programmability comprisingan upper wiring layer capped by a capping material. The interconnectstructure further comprises a second macro having a second e-fuseprogrammability comprising an upper wiring layer capped by a cappingmaterial having interfacial properties which are different than that ofthe first macro.

In a further aspect of the invention, a design structure for e-fuse andinterconnect structures is embodied in a machine-readable medium fordesigning, manufacturing, or testing an integrated circuit. The designstructure comprises a first interconnect structure having a firstinterfacial structure and a second interconnect structure adjacent tothe first structure. The second interconnect structure has secondinterfacial structure different from the first interfacial structure.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention is described in the detailed description whichfollows, in reference to the noted plurality of drawings by way ofnon-limiting examples of exemplary embodiments of the present invention.

FIG. 1 shows the formation of void nucleation sites;

FIG. 2 shows a graph of different void growth rates for cap interfacematerials in accordance with the invention;

FIG. 3 shows a beginning structure and respective processing steps inaccordance with the invention;

FIGS. 4-6 show intermediate structures and respective processing stepsin accordance with the invention;

FIG. 7 shows alternative final structures and respective processingsteps in accordance with the invention;

FIG. 8 shows alternative final structures and respective processingsteps in accordance with the invention;

FIG. 9 shows alternative final structures and respective processingsteps in accordance with the invention;

FIG. 10 shows a final structure with the formation of a void nucleationsite in accordance with the invention; and

FIG. 11 is a flow diagram of a design process used in semiconductordesign, manufacture, and/or test.

DETAILED DESCRIPTION

The invention relates to a design structure, and more particularly, to adesign structure for interconnect structures containing various cappingmaterials for electrical fuses (e-fuses) and other related applications.More specifically, the present invention teaches interconnectstructures, which may be implemented as either normal interconnects ore-fuses. The structures include various capping layer materials at aninterface with a metal wiring layer to provide different interfacialproperties, e.g., EM resistance.

Advantageously, the formation of the interconnect structure and e-fusesof the present invention can be implemented in FEOL, BEOL, and FBEOL,and are compatible with current process flows. The present inventionthus allows the building of e-fuses during normal interconnect processflows, advantageously reducing processing costs for manufacturinge-fuses which are normally fabricated in different process flows. Also,in accordance with different embodiments, depending on the materialsused herein (as discussed in detail below) the e-fuse can be programmedto blow at different current levels. EM effects in the e-fuses of thepresent invention will not cause undesirable hillocks at the anode endof the fuse element.

By way of example, FIG. 1 shows an EM failure mode in an interconnectstructure (or an e-fuse in accordance with the invention). Generally,three major diffusion paths have been identified in the EM failuremechanism. These failure mechanisms can be, for example,

-   -   Cu/capping layer interface;    -   Cu grain boundary; and    -   Cu/barrier (Ta) interface.        The dominant diffusion path depends on the process. For example,        in certain products/processes, the Cu/capping layer interface is        the most critical interface controlling the EM performance.

More specifically, multilayer electronic components comprise multiplelayers of a dielectric material having metallization on each layer inthe form of vias, pads, straps connecting pads to vias and wiring. Viasor other openings in the dielectric layer extend from one layer toanother layer. These openings are filled with a conductive material andelectrically connect the metallization on one layer to the metallizationon another layer and provide for the high-density electronic componentsdevices now used in industry. Metallization metal may be formed using afilling technique such as electroplating, electroless plating, chemicalvapor deposition, physical vapor deposition or a combination of methods.The metal wiring is capped with a dielectric capping layer, which maybe, for example, nitride.

As shown in FIG. 1, at t=0, the electrons are shown to be moving throughthe wiring pattern, However, as time passes, voids (void nucleationsites) begin to form at the interface between the upper wiring layer andthe dielectric capping layer. At t=3, for example, the void becomes solarge that it effectively opens the circuit thus resulting in a failureof the wiring layer. In the case of a fuse, this open circuit is a blownfuse.

FIG. 2 shows a graph of different void growth rates for cap interfacematerials used in accordance with the invention. More specifically, FIG.2 shows a graph of different void growth rates over EM stress time.After extensive experimentation, it has been found that different voidgrowth rates are provided with different Cu/cap interface materials. Asimportant, it was found that EM resistance behaves differently betweendifferent capping materials.

In particular, as shown in FIG. 2, SiN (Si₃N₄) shows the fastest voidgrowth rate over EM stress time. Ta and Ru show a slower void growthrate over EM stress time, with any combination of Co(W, P, B) showingthe slowest void growth rate over EM stress time. Although Ta and Ru andany combination of Co (W, P, B) are shown grouped together,respectively, those of skill in the art should be understood that thesematerials will also have certain variations in void growth rate.

With the data shown in FIG. 2, in a regular interconnect, it is possibleto select a good Cu/capping layer interface (e.g., SiN) to prevent theformation of void nucleation sites. However, it is also desirable toselect poor interface materials (e.g., Ta, Ru and any combination of Co(W, P, B)) for e-fuse applications. As such, in accordance with theinvention, by creating various interfaces which result in different EMresistance during same process flows, it is now possible to fabricate ane-fuse application using process flows of an interconnect structure.This now being possible, the invention contemplates programmable e-fusesusing different capping materials and, in embodiments, by damagingexisting capping materials, any of which exhibit differences in EMresistance when used as a Cu capping layer. Also, the present inventionshould not be limited to the above materials, in that other materials,e.g., Rh and Pt, will provide different void growth rates for capinterface materials in accordance with the invention.

Methods in Accordance with the Invention

FIG. 3 shows a beginning structure and respective processing steps inaccordance with the invention. In particular, FIG. 3 shows identicalmacros, Macro A and Macro B. The Macro A and Macro B will eventually beformed into two or more different structures having differentprogramming efficiencies, implemented as e-fuses or wiring interconnectstructures, for example.

Macro A and Macro B include a dielectric layer 101. The dielectric layer101 may be, for example, SiO₂, Si₃N₄, SiCOH, SiLK, JSR, or porousdielectrics. The dielectric layer 101 could be any interconnect layer inthe structure. In conventional lithographic and etching processes, atrench is formed in the dielectric layer 101. Materials are thendeposited in the trench in conventional deposition processes to form anunderlying metal interconnect 102. For example, a barrier/liner material111 such as TaN is deposited in the trench. A barrier/liner material112, e.g., Ta is deposited over the barrier/liner material 111. A metalinterconnect material 102 is deposited over the barrier/liner material112. The metal interconnect material 102 may be, for example, Cu, Al,Al(Cu) or W to name a few.

Still referring to FIG. 3, a dielectric capping layer 103 is depositedover the structure, in a conventional deposition process such as, forexample, chemical vapor deposition. The dielectric capping layer 103 maybe, for example, Si₃N₄, SiC, SiC(N,H) or other known capping materials.A dielectric layer 104 is deposited over the capping layer 103 in aconventional deposition process. The dielectric layer 104 may be, forexample, SiO₂, Si₃N₄, SiCOH, SiLK, JSR, or porous dielectrics. A hardmask 105 is then deposited over the dielectric layer 104. The hard mask105 may be, for example, SiO₂, Si₃N₄.

Via 108 and trenches 107 and 110 are formed in the structure inaccordance with conventional trench or via formation processes. Forexample, a conventional dual damascene process and a single damasceneprocess can be used to form the features 107, 108, 110. Morespecifically, a conventional lithographic and etching (e.g., RIE)process can be used to form the feature 108 and a second conventionallithographic and etching process can be used to form the features 107,110. The formation of via 108 exposes the underlying interconnect 102.

FIGS. 4-6 show intermediate structures and respective processing stepsin accordance with the invention. In FIG. 4, for example, a liner 201 isformed on the sidewalls of the features 107, 108, 110. The liner 201 maybe, for example, Ta(N), Ti(N), RuTa(N) or IrTa(N). In further processingsteps, copper material is deposited in the structures 107, 108, 110 andover the liner 210 to form a metal interconnect 202. A conventionalchemical mechanical polishing step may be provided to remove any extraconducting material 202 from the structure, e.g., polish the structure.

FIG. 5 shows a dielectric capping layer deposition process in accordancewith the invention. In this processing step, a capping layer 301 isdeposited over the structures (Macro A and Macro B) of FIG. 4. Thecapping layer 301 may be, for example, Si₃N₄ or SiC(N,H). Inembodiments, the capping layer 310 is about 100 Å to 800 Å.

FIG. 6 shows alternate processing steps for Marco B. In particular, inMacro B, the capping layer 301 can be partially or completely removedusing conventional etching processes. In the partial removal scenario,the capping layer 301 preferably is removed over the metal interconnect202, remaining over the dielectric layer 104. In embodiments, Macro Aremains protected by a mask during the etching of the capping layer 301on Macro B.

FIG. 7 shows a selective metal cap deposition on the alternative Macro Bstructures of FIG. 6. During this process, Macro A remains masked. Theselective metal cap deposition 501 of the alternative Macro B structuresinclude, for example, Co(W,P,B), Ru, Ir, Rh or Pt. The metal capdeposition 501 may be about 5 Å to 500 Å. The metal cap depositionprocess could be through CVD, ALD, electro plating, and electrolessplating process. Those of skill in the art will understand that themetal cap deposition 501 may be other materials, depending on thedesired programming efficiencies of the e-fuse. In embodiments, if themetal cap deposition is not selective, it is possible to provide a CMPtouch up process to remove any unwanted deposition metals 501.

FIG. 8 shows a third macro, Macro C, provided in accordance with theinvention. Macro C can be formed simultaneously with Marcos A and B inaccordance with the processing steps of FIGS. 3-6. In this embodiment, ametal cap deposition material 601 is deposited over Macro C, whileMacros A and B remain protected by a mask. The cap deposition material601 on Macro C is different than the metal cap deposition material 501(described with reference to FIG. 7) on Macro B. By way of oneNON-LIMITING example, the metal cap deposition material 501 is Co andthe metal cap deposition material 601 is Ru; although other combinationsof materials (and/or combinations of partial or complete openings) arealso contemplated by the invention.

In the illustrative embodiment shown in FIG. 8, Macro B has a greater EMresistance than Macro C and Macro A. Macro C has a greater EM resistancethan Macro A. As such, Macro A has greater fuse efficiency than Macro Band Macro C. Also, Macro B has greater fuse efficiency than Macro C.

As thus shown in the exemplary representation of FIG. 8, different capmaterials, i.e., different Cu/cap interfaces, results in different EMresistance, i.e. different EM life time. This being the case, Macroswith a poor interface can be used as an e-fuse, and Macros with a goodinterface can be used as the normal interconnect. Also, using anycombination of Macros (and combinations of materials and openings), itis possible to have different e-fuses (with different programmability)made on the same device using substantially the same processing. In thisway, the multi-interface structure may provide circuit programming.

FIG. 9 shows a second embodiment in accordance with the invention. Inthis embodiment, Macros A, B and C have the same dielectric cap material301. However, Macros B and C are subjected to different amount/degree oftreatments, either prior or post the cap material 301 deposition, todegrade the interfacial property between the metal and the dielectriccap layer, e.g., adhesion. The treatment includes radiation sources suchas e-beam, ultraviolet light, visible light, or laser light for alteringthe interfacial property discussed above. FIG. 9 can equally berepresentative of two (or more) Macros, with different treatments or incombination with different treatments and materials as described alreadyherein.

In FIG. 9, area 701 on Macro B is provided with minor damage; whereas,Macro C has serious damage 702. In this illustrative embodiment, Macro Ahas a greater EM resistance than Macro B and Macro C. Macro B has agreater EM resistance than Macro C. As such, Macro C has greater fuseefficiency than Macro B and Macro A. Also, Macro B has greater fuseefficiency than Macro A.

Again, as in the previous embodiments, the advantage of the embodimentof FIG. 9 is to create different Cu/cap interfaces, which results indifferent EM resistance, i.e., different EM life time. The Macros withpoor interface properties can be used as e-fuses, while the Macros withgood interface properties can be used as normal interconnects. Also,this multi-interface structure can have potential on circuitprogramming.

FIG. 10 shows formation of void nucleation sites in structuresfabricated in accordance with the invention. More particular, FIG. 10illustratively shows void formation in the embodiment of FIG. 9. Morespecifically, void formation (i.e., an open circuit) due to EM effectsis shown in the serious damage area 702 of Macro C. The void formationwill effectively blow the fuse.

Design Structure

FIG. 11 shows a block diagram of an exemplary design flow 900 used forexample, in semiconductor design, manufacturing, and/or test. Designflow 900 may vary depending on the type of IC being designed. Forexample, a design flow 900 for building an application specific IC(ASIC) may differ from a design flow 900 for designing a standardcomponent or from a design flow 900 for instantiating the design into aprogrammable array, for example a programmable gate array (PGA) or afield programmable gate array (FPGA) offered by Altera® Inc. or Xilinx®Inc. Design structure 920 is preferably an input to a design process 910and may come from an IP provider, a core developer, or other designcompany or may be generated by the operator of the design flow, or fromother sources. Design structure 920 comprises an embodiment of theinvention as shown in FIGS. 7-9 in the form of schematics or HDL, ahardware-description language (e.g., Verilog, VHDL, C, etc.). Designstructure 920 may be contained on one or more machine-readable media.For example, design structure 920 may be a text file or a graphicalrepresentation of an embodiment of the invention as shown in FIGS. 7-9.Design process 910 preferably synthesizes (or translates) embodiments ofthe invention as shown in FIGS. FIGS. 7-9 into a netlist 980, wherenetlist 980 is, for example, a list of wires, transistors, logic gates,control circuits, I/O, models, etc. that describes the connections toother elements and circuits in an integrated circuit design and recordedon at least one of machine readable media. For example, the medium maybe a CD, a compact flash, other flash memory, a packet of data to besent via the Internet, or other networking suitable means. The synthesismay be an iterative process in which netlist 980 is resynthesized one ormore times depending on design specifications and parameters for thecircuit.

Design process 910 may include using a variety of inputs; for example,inputs from library elements 930 which may house a set of commonly usedelements, circuits, and devices, including models, layouts, and symbolicrepresentations, for a given manufacturing technology (e.g., differenttechnology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 940,characterization data 950, verification data 960, design rules 970, andtest data files 985 (which may include test patterns and other testinginformation). Design process 910 may further include, for example,standard circuit design processes such as timing analysis, verification,design rule checking, place and route operations, etc. One of ordinaryskill in the art of integrated circuit design can appreciate the extentof possible electronic design automation tools and applications used indesign process 910 without deviating from the scope and spirit of theinvention. The design structure of the invention is not limited to anyspecific design flow.

Design process 910 preferably translates an embodiment of the inventionas shown in FIGS. 7-9, along with any additional integrated circuitdesign or data (if applicable), into a second design structure 990.Design structure 990 resides on a storage medium in a data format usedfor the exchange of layout data of integrated circuits and/or symbolicdata format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, mapfiles, or any other suitable format for storing such design structures).Design structure 990 may comprise information such as, for example,symbolic data, map files, test data files, design content files,manufacturing data, layout parameters, wires, levels of metal, vias,shapes, data for routing through the manufacturing line, and any otherdata required by a semiconductor manufacturer to produce embodiments ofthe invention as shown in FIGS. 7-9. Design structure 990 may thenproceed to a stage 995 where, for example, design structure 990:proceeds to tape-out, is released to manufacturing, is released to amask house, is sent to another design house, is sent back to thecustomer, etc.

While the invention has been described in terms of embodiments, those ofskill in the art will recognize that the invention can be practiced withmodifications and in the spirit and scope of the appended claims.

What is claimed is:
 1. An interconnect structure comprising: a firstmacro having a first e-fuse programmability comprising an upper wiringlayer capped by a first capping material; and a second macro having asecond e-fuse programmability comprising an upper wiring layer capped bya second capping material having interfacial properties which aredifferent than that of the first macro.
 2. The interconnect structure ofclaim 1, wherein the first macro further includes an interfacecomprising the upper wiring layer and the first capping material, thesecond macro further includes an interface comprising the upper wiringlayer and the second capping material, and the first capping material isdifferent than the second capping material.
 3. The interconnectstructure of claim 2, wherein the first capping material comprises SiNand the second capping material comprises one of: Co(W,P,B), Ru, Ir, Rhand Pt.
 4. The interconnect structure of claim 2, wherein the secondcapping material and/or the upper wiring layer of the second macro isdamaged to degrade adhesion between the second capping material and theupper wiring layer of the second macro.
 5. The interconnect structure ofclaim 1, wherein the first capping material and the second cappingmaterial is a same material, and the second capping material and/or theupper wiring layer of the second macro is damaged thereby providing adegraded electromigration (EM) resistance than that of the first macro.6. The interconnect structure of claim 5, wherein the second cappingmaterial and/or the upper wiring layer of the second macro is damaged byradiation.
 7. The interconnect structure of claim 6, wherein theradiation is provided by an e-beam, a ultraviolet light, a visiblelight, or a laser light.
 8. The interconnect structure of claim 1,wherein the first macro further includes an interface comprising theupper wiring layer and the first capping material, the second macrofurther includes an interface comprising the upper wiring layer and thesecond capping material, and the second capping material and/or theupper wiring layer of the second macro is damaged thereby exhibitingdegraded interfacial properties between the metal wiring layer and thesecond capping material.
 9. The interconnect structure of claim 1,wherein the first capping material is different than the second cappingmaterial.
 10. The interconnect structure of claim 1, wherein the firstmacro further includes an interface comprising the upper wiring layerand the first capping material, the second macro further includes aninterface comprising the upper wiring layer and the second cappingmaterial, and the interconnect structure further comprises a third macrohaving a third e-fuse programmability comprising an upper wiring layercapped by a third capping material having interfacial properties whichare different than that of the first macro and the second macro.
 11. Adesign structure embodied in a machine readable medium for designing,manufacturing, or testing an integrated circuit, the design structurecomprising: a first macro having a first interfacial structure; and asecond macro having a second interfacial structure, different from thefirst interfacial structure.
 12. The design structure of claim 11,wherein the design structure comprises a netlist.
 13. The designstructure of claim 11, wherein the design structure resides on storagemedium as a data format used for the exchange of layout data ofintegrated circuits.
 14. The design structure of claim 11, wherein thedesign structure resides in a programmable gate array.
 15. The designstructure of claim 11, wherein the first interfacial structure comprisesa first upper wiring layer and a first capping material, and the secondinterfacial structure comprises a second upper wiring layer and a secondcapping material.
 16. The design structure of claim 15, wherein thefirst capping material is different than the second capping material.17. The design structure of claim 15, wherein the first capping materialand the second capping material is a same material, and the secondcapping material and/or the second upper wiring layer is damaged therebyproviding a degraded electromigration (EM) resistance than that of thefirst macro.
 18. The deign structure of claim 15, wherein the secondcapping material and/or the second upper wiring layer is damaged todegrade adhesion between the second capping material and the secondupper wiring layer.